Field of the Invention
The present invention relates to a clock selection circuit and a power supply device equipped with the same.
Background Art
A circuit diagram of a clock selection circuit 400 illustrated in Patent Document 1 is illustrated in FIG. 4 as one example of a related art clock selection circuit.
The clock selection circuit 400 is equipped with a clock switching circuit 1, a main clock monitoring circuit 2, and a shift register 3.
The clock switching circuit 1 is inputted with a first clock f1 and a second clock f2 and outputs either one of the first clock f1 and the second clock f2 as an output clock φ of the clock selection circuit 400, based on an output 4 of the shift register 3.
The shift register 3 includes two D flip-flop circuits 41 and 42. An output Q1 of the D flip-flop circuit 41 is inputted to an input terminal D of the D flip-flop circuit 42. An output Q2 of the D flip-flop circuit 42 is outputted as the output 4 of the shift register 3 and inputted to the clock switching circuit 1.
The main clock monitoring circuit 2 supplies a reset signal R1 generated based on the first clock f1 to respective reset terminals R of the D flip-flop circuits 41 and 42.
The second clock 12 is supplied to respective clock terminals C of the D flip-flop circuits 41 and 42.
Such a related art clock selection circuit 400 outputs the first clock f1 as the output clock φ of the clock selection circuit 400 when the first clock f1 is inputted thereto, and outputs the second clock f2 as the output clock φ when the first clock f1 is stopped.
Thus, according to the related art clock selection circuit 400, the first clock f1 and the second clock 12 can be selectively outputted.
[Patent Document 1] Japanese Patent Application Laid-Open No. Hei 5(1993)-165543